The present invention relates to a semiconductor device and its manufacturing method using a planarization process, particularly making use of the heat treatment of silicide used as a bit line and the reflow of a doped glass.
FIG. 1 is an example of such a semiconductor device manufactured by a conventional process. Particularly, it is a sectional diagram of memory cell part in a semiconductor device.
FIG. 2 is an example of the contact area of a semiconductor device manufactured by a conventional process.
In this drawings, 1 indicates the silicon substrate, 2 the contact layer, 3 the polysilicon gate electrode, 4 the gate oxide film, 5 the doped glass, 6 the silicide bit line, 8 the doped glass, 9 the metal electrode, 10 the low temperature oxide film.
As shown in the drawings, the planarization process is made between the bit line and the metal electrode using only a doped glass, and then the thickness of a doped glass between the bit line and the metal electrode is thinning, and as a consequence, leakage currents are growing.
Also, to decrease the growth of leakage currents between the bit line and the doped glass, the low temperature oxide film is added. This results in a break in the metal electrode in the contact area owing to the difference of the etch rate between the doped glass and the low temperature oxide film.
Therefore, the fact that leakage currents between the bit line and the metal electrode are larger, the breakdown voltage is declines or often shorted is unavoidable. And the problems in the production yield ratio and reliability are also appear.